Comment 14 for bug 568138

I believe this is the relevant commit:

commit e552eb7038a36d9b18860f525aa02875e313fe16
Author: Jesse Barnes <email address hidden>
Date: Wed Apr 21 11:39:23 2010 -0700

    drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge

    Since 965, the hardware has supported the PIPE_CONTROL command, which
    provides fine grained GPU cache flushing control. On recent chipsets,
    this instruction is required for reliable interrupt and sequence number
    reporting in the driver.

    So add support for this instruction, including workarounds, on Ironlake
    and Sandy Bridge hardware.

    https://bugs.freedesktop.org/show_bug.cgi?id=27108

    Signed-off-by: Jesse Barnes <email address hidden>
    Tested-by: Chris Wilson <email address hidden>
    Signed-off-by: Eric Anholt <email address hidden>