Comment 26 for bug 312133
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#26 |
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0e1f616
(Get the code!)
(In reply to comment #14)
> Hi Nuzhdin Urii,
>
> From the log file, I find the reasone may be from too high pixel clock,
> 388.04MHZ of initial mode 2048x1536 exceed our scope.
>
> please try use lower resolution and pixel rate, then paste your log file, which
> are configured in xorg.conf as follow.
>
> Section "Device"
> Identifier "videocard"
> Option "monitor-TV" "TV"
> Option "monitor-LVDS" "LVDS"
>
> ...
> EndSection
>
> Section "Monitor"
> Identifier "LVDS"
> Modeline "1280x1024_60.00" 108.00 1280 1328 1440 1688 1024 1025 1028
> 1066 +hsync +vsync
> Option "PreferredMode" "1280x1024_60.00"
> EndSection
>
>
> Thanks
> Ma Ling
>
ling, for LVDS, timging info for all modes are "fixed up" to the fixed modes in fixup func, so chaning modeline may not help...maybe we can try to dump out more info about the fixed mode the device use (it must be a broken modeline I think )