Comment 96 for bug 256142
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#96 |
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0e1f616
(Get the code!)
The current situation is really surprising: Switching VTs was enough to stop the underrun flood (I didn't even have to restart it). I have now been running X for several hours without a single flicker, while the FBC is still enabled. So I'm not even sure my 64/95 split makes a difference, perhaps the 48/95 would have been sufficient. Could there be some kind of race condition when setting the fifo or FBC that would confuse the chipset?