Comment 41 for bug 661248

@TJ: The BAR configuration registers are in the PCI configuration space. I'm talking about the registeres accessed via memory read/write cycles to the addresses configured there. E.g., open /dev/mem and read at the offset that lspci reports for "Region 0" for your GPU. Alternatively, mmap /sys/devices/path/to/the/gpu/resource0 and read offset 0.