Comment 19 for bug 273329
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#19 |
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0e1f616
(Get the code!)
(In reply to comment #13)
> Traditionally, the zbuffer layout is different on low end/IGP variants (i.e.
> those that are TCL-less). That is the case for r100/r200 and that would be
> consistent with the fact that this bug is only seen on those chips, so I'd
> wager this geenralizes to r300 as well. Did anyone dig into that possibility ?
> Basically you'd just need to fix the span code in mesa.
But tile translation should be handled by the chip itself (except there was a bug with the tcl-less r100), by use of the tiling regions. This should work the same no matter what the layout actually is. Unless the surface bits would have different meaning for some r300 based chips or there are some other options with tile configuration...