Comment 10 for bug 177646

According to this spec regarding the Celeron 500 series, covering at least the 540 (not sure about the M 530):
 http://download.intel.com/design/mobile/datashts/31766603.pdf

the architecture does support clock and power control, through the C-states. It seems not to be only a thermal solution, but what do I know!

Is C-states control the throttling/thermal technique you are talking about?
And is C-state handling taken care of, in the current Hardy kernel?

Sorry for my (maybe) stupid questions!