mia ftbfs on armhf

Created attachment 158
preprocessed source

seen with Linaro 4.8 and Linaro 4.9, configured for armhf, armv7, thumb, binutils trunk:

$ g++ -std=c++11 -c -O2 productcache.ii
/tmp/ccpPnwKE.s: Assembler messages:
/tmp/ccpPnwKE.s:81: Error: thumb conditional instruction should be in IT block -- `strexeq r2,r0,[r4]'
/tmp/ccpPnwKE.s:187: Error: thumb conditional instruction should be in IT block -- `strexeq r0,r1,[r4]'

no workaround known.

It is a problem with the inline asm (meant for arm and not thumb mode) in the source code and seems to be a wide spread problem in existing sr. I don't think an we can do anything from the tool-chain as such. Problem is in:

int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand )
{
    int32_t oldval, res;

    __asm__ __volatile__("dmb ish": : :"memory");

    do {
    __asm__ __volatile__(
        "ldrex %1, [%3]\n"
        "mov %0, #0\n"
        "cmp %1, %4\n"
        "strexeq %0, %5, [%3]\n"
        : "=&r" (res), "=&r" (oldval), "+Qo" (*(volatile int32_t*)ptr)
        : "r" ((int32_t *)ptr), "Ir" (comparand), "r" (value)
        : "cc");
    } while (res);

    __asm__ __volatile__("dmb ish": : :"memory");

    return oldval;
}

Adding IT block in arm mode is ok and ignored. It might be better to fix the package that way.

Also found:
http://lists.linaro.org/pipermail/linaro-toolchain/2010-July/000035.html